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50h5205 sa14-4664-01 revised 9/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 1 of 14 IBM041814PQKB preliminary 64k x 18 burst sram features ? 64k x 18 synchronous burst mode sram ? 0.5 m cmos technology ? synchronous burst mode of operation compati- ble with powerpc tm processors ? lvttl i/o compatible with common i/o ? single +3.3 v 5% power supply and ground ? registered addresses, data ins and control signals ? 5 v tolerant i/o ? asynchronous output enable ? self-timed write operation and byte write capability ? low power dissipation - 1.1 w active at 83mhz - 90 mw standby ? 100 pin thin quad flat pack description ibm microelectronics 1m sram is a synchronous burstable, high performance cmos static ram that is versatile, wide i/o, and achieves 8 nsec access. a single clock is used to initiate the read/write opera- tion and all internal operations are self-timed. at the rising edge of the clock, all addresses, data ins and control signals are registered internally. burst mode operation, compatible with powerpc tm processors sequence, is accomplished by integrating input reg- isters, internal 2-bit burst counter and high speed sram in a single chip. burst reads are initiated with either adsp or adsc being low with a valid address during the rising edge of clock. data from this address plus the three subsequent addresses will be output. the chip is operated with a single +3.3 v power supply and is compatible with lvttl i/o interfaces. ibm043614pqk32k x 36burst (powerpc), tqfp package.
IBM041814PQKB 64k x 18 burst sram preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 2 of 14 50h5205 sa14-4664-01 revised 9/97 x18 tqfp pin array layout pin description a0-a15 address input adsp address status processor dqa - dqb data input/output (1-8 , 9-16) adsc address status controller clk clock adv burst advance control wea write enable, byte a (1 to 8 & dqp1) cs adsp - gated chip select web write enable, byte b (9 to 16 & dqp2) v dd power supply (+3.3v) oe output enable v ss ground cs2 , cs2 chip selects v ddq output power supply (+3.3v) dqp1,dqp2 parity bits for byte a, and byte b. nc no connect nc 1 nc 2 nc 3 nc 4 nc 5 nc 6 nc 7 dq9 8 dq10 9 vss 10 vddq 11 dq11 12 dq12 13 nc 14 v dd 15 nc 16 vss 17 dq13 18 dq14 19 vddq 20 vss 21 dq15 22 dq16 23 dqp2 24 nc 25 nc 26 nc 27 nc 28 nc 29 nc 30 nc 31 a5 32 a4 33 a3 34 a2 35 a1 36 a0 37 nc 38 nc 39 vss 40 vdd 41 nc 42 nc 43 a15 44 a14 45 a13 46 a12 47 a11 48 nc 49 nc 50 80 a10 79 nc 78 nc 77 nc 76 nc 75 nc 74 dqp1 73 dq8 72 dq7 71 vss 70 vddq 69 dq6 68 dq5 67 vss 66 nc 65 vdd 64 nc 63 dq4 62 dq3 61 vddq 60 vss 59 dq2 58 dq1 57 nc 56 nc 55 nc 54 nc 53 nc 52 nc 51 nc 100 a6 99 a7 98 cs 97 cs2 96 nc 95 nc 94 web 93 wea 92 cs2 91 vdd 90 vss 89 clk 88 nc 87 nc 86 oe 85 adsc 84 adsp 83 ad v 82 a8 81 a9
IBM041814PQKB preliminary 64k x 18 burst sram 50h5205 sa14-4664-01 revised 9/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 3 of 14 block diagram ordering information part number organization speed leads notes IBM041814PQKB-8 64k x 18 8 ns access / 12 ns cycle 100 pin tqfp IBM041814PQKB-9 64k x 18 9 ns access / 12 ns cycle 100 pin tqfp IBM041814PQKB-10 64k x 18 10 ns access / 12 ns cycle 100 pin tqfp IBM041814PQKB-11 64k x 18 11 ns access / 12 ns cycle 100 pin tqfp 64k x 18 array a0 - a15 row address register column address register burst binary counter byte write register clear byte write register select registers adsp a2 - a9 a10 - a15 a0 a1 adsc clk cs wea oe dq0 - dq9 - dq17 dq8 web adv sa0 sa1 cs cs2 cs2
IBM041814PQKB 64k x 18 burst sram preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 4 of 14 50h5205 sa14-4664-01 revised 9/97 burst sram clock truth table clk cs2 cs2 cs adsp adsc ad v we oe dq operation l ? h hxl lxxxx high-z deselected cycle l ? h xl l lxxxx high-z deselected cycle l ? h h x x x l x x x high-z deselected cycle l ? h x l x x l x x x high-z deselected cycle l ? h lhl lxxxlq read from external address, begin burst l ? h l h l l x x x h high-z read from external address, begin burst l ? h lhlhlxhlq read from external address, begin burst l ? h lhlhlxlxd write to external address, begin burst l ? h xxxhhlhlq read from next add., continue burst l ? h xxxhhl lxd write to next add., continue burst l ? h xxxhhhhlq read from current add., suspend burst l ? h xxxhhhlxd write to current add., suspend burst l ? h x x h x l x x x high-z deselect cycle l ? h xxhxhlhlq read from next add., continue burst l ? h xxhxhl lxd write to next add., continue burst l ? h xxhxhhhlq read from current add., suspend burst l ? h xxhxhhlxd write to current add., suspend burst 1. for a write operation preceded by a read cycle, oe must be high early enough to allow input data setup, and must be kept high through input data hold time. 2. we refers to we a, we b. 3. adsp is gated by cs, and cs is used to block adsp when cs = v ih , as required in applications using processor address pipelin- ing. 4. all addresses, data in and control signals are registered on the rising edge of clk. burst sequence truth table external address a15-a2 (a1,a0) notes (0,0) (0,1) (1,0) (1,1) 1st access a15-a2 (0,0) (0,1) (1,0) (1,1) 2nd access a15-a2 (0,1) (1,0) (1,1) (0,0) 3rd access a15-a2 (1,0) (1,1) (0,0) (0,1) 4th access a15-a2 (1,1) (0,0) (0,1) (1,0)
IBM041814PQKB preliminary 64k x 18 burst sram 50h5205 sa14-4664-01 revised 9/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 5 of 14 write enable truth table we a we b byte written notes h h read all bytes l l write all bytes lh write byte a (d in 0 - 8) hl write byte b (d in 9 - 17) absolute maximum ratings parameter symbol rating units notes power supply voltage v dd -0.5 to 4.6 v 1 input voltage v in -0.5 to 6.0 v 1 output voltage v out -0.5 to v dd +0.5 v1 operating temperature t opr 0 to +70 c 1 storage temperature t stg -55 to +125 c 1 power dissipation p d 2.0 w 1 short circuit output current i out 50 ma 1 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operati onal sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect r eli- ability. recommended dc operating conditions (t a =0 to 70 c) parameter symbol min. typ. max. units notes supply voltage v dd 3.135 3.3 3.465 v 1, 4 input high voltage v ih 2.2 5.5 v 1, 2, 4 input low voltage v il -0.3 0.8 v 1, 3, 4 output current i out 5 8ma4 1. all voltages referenced to v ss . all v dd and v ss pins must be connected. 2. v ih (max)dc = 5.5 v, v ih (max)ac = 6.0 v (pulse width 4.0ns). 3. v il (min)dc = - 0.3 v, v il (min)ac= -1.5 v (pulse width 4.0ns). 4. input voltage levels are tested to the following dc conditions: 1 microsecond cycle and 200 nanosecond set-up and hold times. capacitance (t a =0 to +70 c, v dd =3.3v 5%, f=1mhz) parameter symbol test condition max units notes input capacitance c in v in = 0v 5pf data i/o capacitance (dq0-dq17) c out v out = 0v 5pf
IBM041814PQKB 64k x 18 burst sram preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 6 of 14 50h5205 sa14-4664-01 revised 9/97 dc electrical characteristics (t a = 0 to +70 c, v dd =3.3v 5%) parameter symbol min. max. units notes operating current average power supply operating current ( oe = v ih , i out = 0) i dd 12 300 ma 2, 3 standby current power supply standby current ( cs2 = v ih or cs2 = v il or cs = v il all other inputs = v ih or v il , i out. = 0 clock @ 83mhz) i sb 25 ma 1, 3 input leakage current input leakage current, any input (v in = 0 &v dd ) i li +1 m a 4 output leakage current (v out =0 &v dd , oe = v ih ) i lo +1 m a output high level output h level voltage (i oh =-8ma @ 2.4v) v oh 2.4 v output low level output l level voltage (i ol =+8ma @ 0.4v) v ol 0.4 v 1. i sb = stand-by current. 2. i dd = selected current. 3. i out = chip output current. 4. the input leakage current for 5.5v input is 200 m a for clk, chip selects, and output enable. other inputs have 100 m a of leakage current at 5.5v. ac test conditions (t a =0 to +70 c, v dd =3.3v 5%) parameter symbol conditions units notes input pulse high level v ih 3.0 v input pulse low level v il 0.0 v input rise time t r 2.0 ns input fall time t f 2.0 ns input and output timing reference level 1.5 v output load conditions 1 1. see ac test loading figure on page 8.
IBM041814PQKB preliminary 64k x 18 burst sram 50h5205 sa14-4664-01 revised 9/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 7 of 14 ac characteristics (t a =0 to +70 c, v dd =3.3v 5%, units in nsec) parameter symbol -8 -9 -10 -11 notes min. max. min. max. min. max. min. max. cycle time t cycle 12.0 12.0 12.0 12.0 clock pulse high t ch 3.0 3.0 3.0 3.0 clock pulse low t cl 3.0 3.0 3.0 3.0 clock to output valid t cq 8.0 9.0 10.0 11.0 3 address status controller setup time t adscs 2.5 2.5 2.5 2.5 address status controller hold time t adsch 0.5 0.5 0.5 0.5 address status processor setup time t adsps 2.5 2.5 2.5 2.5 address status processor hold time t adsph 0.5 0.5 0.5 0.5 advance setup time t advs 2.5 2.5 2.5 2.5 advance hold time t advh 0.5 0.5 0.5 0.5 address setup time t as 2.5 2.5 2.5 2.5 address hold time t ah 0.5 0.5 0.5 0.5 chip selects setup time t css 2.5 2.5 2.5 2.5 chip selects hold time t csh 0.5 0.5 0.5 0.5 write enables setup time t wes 2.5 2.5 2.5 2.5 write enables hold time t weh 0.5 0.5 0.5 0.5 data in setup time t ds 2.5 2.5 2.5 2.5 data in hold time t dh 0.5 0.5 0.5 0.5 data out hold time t cqx 3.0 3.0 3.0 3.0 3 clock high to output high-z t chz 5.0 5.0 5.5 5.5 1, 2, 4 clock high to output active t clz 2.5 2.5 2.5 2.5 1, 2, 4 output enable to high-z t ohz 2.0 5.0 2.0 5.5 2.0 6.0 2.0 6.5 1, 4 output enable to low-z t olz 0.25 0.25 0.25 0.25 1, 4 output enable to output valid t oq 4.0 5.0 5.0 6.0 3 1. transitions are measured 200 mv from steady state voltage. 2. at any given voltage and temperature, t chz (max) is always less than t ctz (min) for a given device and from device to device. for any read cycle preceded by a write or deselect cycle, the data bus will transition glitch-free from high-z to new ram data. 3. see ac test loading ?gure 1 on page 8. 4. see ac test loading ?gure 2 on page 8.
IBM041814PQKB 64k x 18 burst sram preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 8 of 14 50h5205 sa14-4664-01 revised 9/97 ac test loading 50 w vl = 1.5 v 50 w dq fig. 1 test equivalent load 0.0 0.5 1.0 1.5 2.0 2.5 3.0 015 45 30 75 105 picofarads -0.5 -1.0 60 90 nanoseconds the derating curve above is for a purely capacitive load on the output driver. for example, a part speci?ed at 8ns access time will behave as though it has an 8.5 ns access time if a 30 pf load with no dc component was attached to the output driver. the access times guaran- teed in the datasheets are based on a 50 ohm terminated test load. for unterminated loads the derating curve should be used. this curve is based on nominal process conditions with worst case parameters v cc = 3.14 v, t a = 70 c . 30 pf output capacitive load derating curve 351 w dq fig. 2 test equivalent load 5 pf + 3.3 v 317 w
IBM041814PQKB preliminary 64k x 18 burst sram 50h5205 sa14-4664-01 revised 9/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 9 of 14 timing diagram (burst read) clk oe a1 a2 addr adv adsc adsp wea, web cs2 dq t cycle t ch t cl t adsps t adsph t adscs t adsch t advs t advh t as t ah t ah t as t weh t wes t csh t css t css t csh t olz t oq t cq q1(a) q2(a) q2(b) q2(c) t cqx t cq q2(d) t ohz t cq t cqx cs2 cs notes: 1. q1(a) and q2(a) refer to data written to address a1 and a2. 2. q2(b), q2(c) and q2(d) refer to data written to subsequent internal burst counter addresses.
IBM041814PQKB 64k x 18 burst sram preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 10 of 14 50h5205 sa14-4664-01 revised 9/97 timing diagram (burst write) clk oe a2 addr adv adsc adsp cs2 dq t cycle t ch t cl a1 d1(a) d2(a) d2(b) d2(b) t adsps t adsph t adsch t adscs t advh t advs t advh t advs t ah t as t as t ah t weh t wes t css t csh t ohz t dh t ds t chz t ds t dh t ds t ds t dh t dh t css t csh cs2 cs notes: 1. d1(a) and d2(a) refer to data written to address a1 and a2. 2. d2(b) refers to data written to a subsequent internal burst counter address. 3. wea, web are dont cares when adsp is sampled low. t clz wea, web
IBM041814PQKB preliminary 64k x 18 burst sram 50h5205 sa14-4664-01 revised 9/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 11 of 14 100 pin tqfp package diagram note: all dimensions in millimeters 20.00 0.10 22.00 0.20 14.00 0 .10 16.00 0.20 pin 1 i.d. 6? 4? 1.60 max 0.25 0.60 + 0.15/-0.10 standoff lead coplanarity seating plane 0.10 max rad 0.20 typ 0.05/0.15(min/max) 0?- 7? 12? typ 12? typ 1.40 0.10 0.05/0.15 (min/max) 1.60 max 0.65 basic 0.30 0.05
IBM041814PQKB 64k x 18 burst sram preliminary ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 12 of 14 50h5205 sa14-4664-01 revised 9/97 the ibm041812pqk has the pins connected in the manner indicated in the current connections (x18) and is also jedec complaint. future connections refers to the evolution on the jedec standard for subsequent part numbers. connect compatibility for 64k x18 and future 64k x 16 & 64k x 18 tqfp pin # current connections (x18) future connections (x16 & x18) function 4,27,54,77 nc v ddq output power supply 5,26,55,76 nc v ss ground 14 nc low or high, nc for most vendors but low or high to comply to the jedec standard. ft , flow thru or pipeline function, tie low for flow thru, high for pipeline 24 dqp2 nc or dq in x18 parity bit for second byte 31 nc low or high lbo , linear burst order, this pin must be tied low for linear(powerpc), high for interleave (pentium) 64 nc low or high. low allows normal opera- tion. zz , asynchronous sleep mode, tie to ground for normal function, v ddq for sleep mode (low power state) 74 dqp1 nc or dq in x18 parity bit for first byte 87 nc low or bwe, tie low if function not used byte write enable, allows individual bytes to be written. 88 nc low or gw, tie high if function not used global write enable, allows write of all bytes to occur with single pin.
IBM041814PQKB preliminary 64k x 18 burst sram 50h5205 sa14-4664-01 revised 9/97 ?ibm corporation. all rights reserved. use is further subject to the provisions at the end of this document. page 13 of 14 revision log rev contents of modi?cation 7/95 initial release of the 64k x 18 (8/9/10/11) tqfp burst mode application spec. 9/97 updated part numbers to add die revision character. this new datasheet does not reflect a die revision
intern ational business machines corp.1997 printed in the united states of america all rights reserved ibm and the ibm logo are registered trademarks of the ibm corporation. this document may contain preliminary information and is subject to change by ibm without notice. ibm assumes no responsibility or liability for any use of the information contained herein. nothing in this document shall operate as an express or implied lice nse or indemnity under the intellectual property rights of ibm or third parties. the products described in this document are not inten ded for use in implantation or other direct life support applications where malfunction may result in direct physical harm or injury to persons. no warranties of any kind, including, but not limited to, the implied warranties of merchantability or fitness for a particular purpose, are offered in this document . for more information contact your ibm microelectronics sales representative or visit us on world wide web at http://www.chips.ibm.com ibm microelectronics manufacturing is iso 9000 compliant. a

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